The present invention relates generally to a microcomputer. More specifically, the invention relates to an improved instruction cycle in a microcomputer which may help speed up microcomputer processing.
Modern monolithic microcomputers often employ a pipe-lined architecture which allow fetch cycles and instruction execution cycles to overlap. In the fetch cycle, instructions are fetched from memory. Each instruction consists of an operation code (OP code) which is stored in read-only-memory, such as programmable read-only-memory (PROM), and an operand, also stored in ROM, which may point to a variable value stored in random-access memory (RAM). In conventional pipe-line architectures, the OP code fetch and the operand fetch are performed in different instruction execution cycles, hereafter referred to as xe2x80x9cinstruction cyclesxe2x80x9d. For example, in order to fetch a 2-byte instruction including a 1-byte OP code and a 1-byte operand in a 4-bit microcomputer, 2 instruction cycles are required. Therefore, in this case, each instruction cycle takes three machine clock cycles. This conventional pipe-line architecture is not satisfactorily efficient.
In general, the fetch cycle for fetching OP codes or operands is shorter than the instruction cycle. This means that there is a period in the execution cycle during which no fetching is being performed. If the next instruction component can be fetched during this period, run-time can be shortened.
Therefore, it is an object of the present invention to provide a microcomputer with an improved fetch cycle for shortening the instruction cycle.
In order to accomplish the aforementioned and other objects, a microcomputer, according to the present invention, includes an instruction decoder and a program counter. The instruction decoder decodes fetched instructions and outputs a control signal ordering execution of the fetched instruction. The control signal from the instruction decoder includes a component controlling fetch cycles which triggers a fetch cycle at the beginning of each instruction cycle to fetch the operand for the instruction currently being executed and midway through each instruction cycle to fetch the OP code for the next instruction.
The program counter is responsive to the triggering of each fetch cycle to increment its counter value so as to keep the counter value consistent with the address being accessed in each fetch cycle.
According to one aspect of the invention, a method of operating a microprocessor with a pipe-lined architecture, which allows the instruction data for a later instruction execution cycle to be fetched from memory during a current instruction cycle, comprising the steps of:
preprogramming instruction operation codes (OP codes) for instructions requiring more than 1 byte of instruction data with additional information requesting time-compressed fetching of instruction data; and
fetching more than 1 byte of instruction data from memory during the instruction cycle immediately following a request for time-compressed fetch.
The instruction data consists of one OP code byte and one operand byte and the OP code byte is fetched immediately before the onset of an instruction cycle, the fetching step comprising the step of fetching the operand byte associated with the fetched or code byte concurrently with the onset of the instruction cycle. In the alternative, the instruction data consists of one OP code byte and two operand bytes and the OP code byte is fetched immediately before the onset of a first instruction, the fetching step comprising the steps of fetching a first operand byte associated with the fetched OP code byte concurrently with the onset of the first instruction cycle and of fetching a second operand byte associated with the first operand byte during the first instruction cycle following fetching of the first operand byte.
The method further comprising the step of executing the instruction specified by the OP code and operand bytes in the instruction cycle immediately prior to which the OP code byte was fetched.